1. Field of the Invention
The present invention relates to semiconductor integrated circuit (IC) chips which can be tailored to produce a fuse. The invention further relates to a method of making an improved non-corrosive resistive structure.
2. Related Art
Fuses can be used in semiconductor chips to provide redundancy, electrical chip identification and customization of function. For designs having three (or more) layers of wiring, the fuses are typically formed from a segment of one of the wiring layers, e.g., the xe2x80x9clast metalxe2x80x9d (LM) or xe2x80x9clast metal minus onexe2x80x9d (LMxe2x88x921) wiring layer. Fusing, i.e., the deletion of a segment of metal fuse line, is accomplished by exposing the segment of metal fuse line to a short, high intensity pulse of xe2x80x9clightxe2x80x9d from an infra-red (IR) laser. The metal line absorbs energy, melts and expands, and ruptures any overlain passivation layer. The molten metal then boils or vaporizes out of its oxide surroundings, disrupting line continuity and causing high electrical resistance. Metals exposed by this laser deletion process can corrode possibly leading to undesirable reconnection of a fuse link.
Semiconductor integrated circuits are formed in a body of semiconductor material having active regions which are joined in a desired circuit configuration by a plurality of wiring layers laid down on the surface of the body.
In the manufacture of the circuits, wiring layers are deposited and defined and interconnected with conductive vias through a series of well known photolithography and metal etching steps. Each such wiring level can be coated with a layer of a glassy protective material, known as a passivation layer, which protects and insulates the wiring of each layer. The creation of integrated circuits with such multiple wiring layers is well known to the semiconductor art.
In some circuits, such as, e.g., CMOS logic circuits, the fuses designed in the circuit are often formed in regular arrays in the upper most layers of wiring and in a position such that other wiring is not placed immediately over the fuses. In such arrays the fuses are often aligned in parallel rows and placed as closely together as is possible. By opening selected ones of these fuses the logic elements of the circuits can be arranged in different combinations to perform different logic functions.
These fuses are typically opened by applying a laser pulse of sufficient size, duration and power as to superheat and vaporize the metal forming the fuse. This superheating of the fuse and its vaporization fractures and blows away a portion of the overlying glassy protective layer creating a saucer shaped crater in the protective layer. When the protective layer ruptures, cracks can radiate outwardly causing additional damage such as breakage of or the uncovering of adjacent elements. Such uncovering of the adjacent elements can cause subsequent corrosion and premature failure of the circuit.
It is desirable that in future generation integrated circuits, such as, e.g., sub-0.25 xcexcm complimentary metal oxide semiconductor (CMOS) back end of line (BEOL), that copper (Cu) wiring be employed to meet BEOL resistor capacitor (RC) delay performance requirements. During stressing of copper fuses, such as under conditions of, e.g., in 85 degrees celsius (C) temperature, 85% relative humidity with electrical bias stressing, copper fuses can corrode. This corrosion may extend through multiple via levels if a Tantalum Nitride/Tantalum (TaN/Ta) liner does not act as a corrosion stop. The byproduct of this corrosion can completely cover the blown fuse area which can create an undesirable resistive leakage path between blown fuses. Known methods of reducing or eliminating this defect include using aluminum wiring and passivating the copper fuse after fuseblow. However, adding an aluminum wiring level reduces the electrical performance of the device and adding a passivation layer after fuseblow increases cost and complexity. An improved method to reduce or eliminate corrosion of exposed copper wiring is desired.
The reader is referred to the following patents related to fuses including:
xe2x80x9cFusible Links with Improved Interconnect Structure,xe2x80x9d U.S. Pat. No. 5,760,674;
xe2x80x9cArray Fuse Damage Protection Devices and Fabrication Method,xe2x80x9d U.S. Pat. No. 5,420,455, to Richard A. Gilmour, et al.;
xe2x80x9cIntegrated Pad and Fuse Structure for Planar Copper Metallurgy,xe2x80x9d U.S. Pat. No. 5,731,624, to William T. Motsiff, et al.;
xe2x80x9cMethod of making a multilayer thin film structure,xe2x80x9d U.S. Pat. No. 5,266,446, to Kenneth Chang, et al.; the contents of which are incorporated herein by reference in their entirety.
The reader is also referred to several articles, published patent documents and patents:
Anon., xe2x80x9cFuse Structure for Wide Fuse Materials Choice,xe2x80x9d IBM Technical Disclosure Bulletin, Vol. 32, No. 3A, August 1989, pp. 438-439;
Anon., xe2x80x9cOptimum Metal Line Structures for Memory Array and Support Circuits,xe2x80x9d IBM Technical Disclosure Bulletin, Vol. 30, No. 12, May 1988, pp. 218-219;
Anon., xe2x80x9cMethod to Incorporate Three Sets of Pattern Information in Two Photo-Masking Steps,xe2x80x9d IBM Technical Disclosure Bulletin, Vol. 32, No.8A, January 1990, pp. 170-171;
xe2x80x9cStructure and Method of Making Alpha-Ta in Thin Films,xe2x80x9d U.S. Pat. No. 5,281,485 to E. G. Colgan;
European Published Application EP 751566 A2, xe2x80x9cA Thin-Film Metal Barrier for Electrical Connections,xe2x80x9d to C. Cabral er al.
C. -K. Hu et al., xe2x80x9cDiffusion Barrier Studies for Cu,xe2x80x9d Proc. V-MIC, 1986, pp. 181-187;
C. -H. HU et al., xe2x80x9cCopper-Polyimide Wiring Technology for VLSI Circuits,xe2x80x9d Proc. Material Research soc., 1990, pp. 369-373; and
D. Edelstein et al., xe2x80x9cFull Coper Wiring in a Sub-0.25 xcexcm CMOS ULSI Technology,xe2x80x9d Tech. Dig. IEEE Int. Electr. Dev. Mtg. 1997, pp. 773-776, the contents of which are incorporated herein by reference in their entirety.
Resistor elements are important for peripheral and internal circuits. Resistor elements can be used in internal circuits in, e.g., voltage regulators, reference bias circuits, and other applications. Resistor elements can be used in peripheral circuits in receiver and driver circuits for impedance matching, noise/ring-back dampening, resistor ballasting, overvoltage dampening and other applications. In electrostatic discharge (ESD) networks, resistors can be used in resistor capacitor (RC) coupled n-type field effect transistors (NFETs), integrated with metal oxide semiconductor FETs (MOSFETs) for resistor ballasting, and a plurality of other applications.
Many materials used as resistors are good in a functional regime but inadequate for ESD robustness or precision linear applications. Diffused resistors are commonly used in circuit applications, yet can have many disadvantages. Polysilicon film resistors, and diffused implanted resistors can have many concerns in high voltage and high current regimes. N-well, n-diffusion and buried resistors (BR) can be used in many circuit applications. Polysilicon resistors can also have reliability concerns. Polysilicon resistors can exhibit a xe2x80x9cspaghetti effectxe2x80x9d at high voltage stress. Under high voltage stress, polysilicon resistors can have a tendency to change resistance values causing mis-function of circuit and ESD applications.
N-well, n-diffusion and buried resistors (BR) can be used in many circuit applications. Diffused resistors can add extra capacitance to a circuit. This extra capacitance can be disadvantageous to receiver performance and driver capacitance loading. For analog, radio frequency CMOS and high performance applications, capacitance can be a concern. Diffused resistors can also be involved in ringing phenomenon (ring-back), undershoot phenomena, and latchup. For solid state transistor logic (SSTL) circuit applications where xe2x80x9ccritical dampeningxe2x80x9d is needed, e.g., in input/output (I/O) circuits, diffused elements can be detrimental to the ringing as they pass current in negative undershoot. N-well, n-diffusion, and buried resistors (BRs) can also form a parasitic npn structure that can create unwanted ESD and functional parasitic devices. As a result, ground rules can be expanded to address these parasitic devices. The resistor elements can become a large percentage of the I/O circuit area between the physical structure and the ground rule spaces required. Diffused resistors can also have charged device model (CDM) concerns. In a CDM test mode, for example, diffused resistors can be actively involved, leading to unwanted parasitic devices.
What is needed then, is a resistor that has low capacitance, high resistance, high linearity with voltage and temperature, is physically small, and has a high melting temperature. It is also desired that the improved resistor not interact with a silicon surface of a substrate. It is desirable that the resistive element be usable in applications requiring insensitivity to voltage stressing, electrical overstress (EOS) and electrostatic discharge (ESD) phenomenon.
A metal structure formed on a semiconductor substrate including a first portion including a lower layer and an upper layer, the lower layer having a higher electrical resistivity than the upper layer, the upper layer having horizontal and vertical surfaces that are in contact with the lower layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the lower layer, the lower layer not being in contact with the horizontal and vertical surfaces of the upper layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element.
The present invention can include a method of fabricating a corrosion resistant fuse including the steps of lithographically patterning, etching, depositing a refractory liner. (which can act as a resistor), depositing copper and using chemical mechanical polishing (CMP) to damascene a last metal (LM) wiring level and fuses, lithographically patterning one or more openings over the fuse, removing exposed copper using an etchant that is selective to copper and does not attack the liner, such as, e.g., aqueous ammonium persulfate, or a mixture of sulfuric acid, hydrogen peroxide, and water, removing resist and depositing final passivation films; completing processing defining terminal metal contact holes in final passivation films, and electrically testing and laser deleting the fuse, wherein the fuse is comprised of at least one of a segment of liner and a segment of the copper LM line isolated on at least one side by a xe2x80x9cliner onlyxe2x80x9d structure.
An advantage of the present invention is that the laser deleted region is isolated from the remainder of the copper circuitry by links of fully passivated, corrosion resistant refractory material, such as, e.g., TaN/Ta. In one embodiment of the invention, the fuse can be a portion of the TaN/Ta link, and in another embodiment, the fuse can be an appropriately sized portion of a TaN/Ta/Cu line which is adjacent to the TaN/Ta links. The structure of the present invention intrinsically eliminates the possibility of spreading of deleted fuse associated corrosion into the chip wiring or bridging of the deleted region.
Another advantageous feature of the present invention is that the fully passivated, corrosion resistant refractory material, such as, e.g., TaN/Ta links can be used as resistors. The resistor structure has low capacitance, high resistance, high linearity with temperature and voltage, is physically small, and has a high melting temperature.
An advantage of a back end of line resistor (BEOL) with high melting melting temperatures, provided by refractory metals is that it provides electrostatic discharge (ESD) protection.
The power to failure (Pf/A) of an interconnect is proportional to the square root of the thermal conductivity (K), the heat capacity (Cp), and the mass density (xcfx81), times the melting temperature of the interconnect (Tmelting), divided by the pulse width (xcfx841/2), see Table 1, below. Material (i.e., wire) that has a higher melting temperature will be more robust from over voltage and over current protection as well as ESD phenomena.
Having resistors in series with sensitive circuits can also be advantageous to prevent over voltage of the peripheral circuits in a semiconductor chip.
This invention is a resistor structure placed between the pads and the ESD device. The device can also be physically a fuse.
A feature of the invention provides a structure, a method and circuit applications for applications which desire insensitivity to voltage stress, electrical overstress (EOS) and electrostatic discharge (ESD) phenomena.
Another feature of the resistor element of the invention is that it can be used for mixed voltage, analog/digital and mixed signal applications.
Another feature of the resistor element of the invention, if using a back end of line (BEOL) resistor, is that the resistor also has low capacitance, so that if it is in a low capacitance material or silicon dioxide, it has significantly lower capacitance than silicon based resistor structures.
Thus, another feature of the invention uses the interconnect as a resistor as well.
Another feature of the resistor is as the interconnect temperature increases, the resistance increases, (e.g., R(T)=Ro(1+xcex1T)) increasing the ballasting at high currents. Yet another advantage of Ta, particularly xcex1-Ta, is that reasonably sized resistors, such as, e.g., 50 ohm resistors, can be formed.
The typical resistor can be used for impedance matching, and for resistor ballasting. The resistor ballasting concept takes a multi-finger element and digitate it into multiple elements and put resistors in parallel. The invention can provide resistor ballasting in a multi-element cell which allows, when the resistors are placed in parallel, to place resistors of significantly higher value to prevent electrical overload in one of the sub cells.
A feature of the resistor element of the invention is that it has very low skin effect concerns for high frequency applications.
Another feature of the invention provides a resistor element having a high critical current-density-to-failure (Jcrit).
A method of forming the resistor structure can include a damascene process. The resistor is consistent with the manner in which damascene structures are formed. For example, in copper by using a trough, followed by a refractory metal deposition. An embodiment of the invention forms a resistor element using a single damascene process. Another embodiment includes a single damascene process where the resistor includes a trough. Another embodiment includes a single damascene process where the resistor includes a trough, a tungsten (W) contact, and a W film trough. An embodiment of the invention forms a resistor element using a dual-damascene process. Another embodiment includes a dual-damascene process where the resistor includes a trough and a via. Another embodiment includes a dual-damascene process where the resistor includes a trough, a via and a second trough. Another embodiment includes a dual-damascene process where the resistor includes a trough, a via and a second trough, a W contact and a W film trough.
An example method of the present invention includes the steps of forming a resistor by a damascene process, including defining a trough, depositing a highly resistive film, depositing a second film, polishing, and etching out the second film to obtain a resistor structure. In one embodiment of the invention, the first film can be tantalum, xcex1-Ta, tantalum nitride, or another liner/diffusion barrier material. In another embodiment of the invention, the second film can be a conductive film such as, e.g., copper.
Another example method of the present invention includes the steps of forming a resistor by a dual-damascene process, including defining a trough and via, depositing a highly resistive film, depositing a second film, polishing, and etching out the second film to obtain a resistor structure. In one embodiment of the invention, the first film can be tantalum, tantalum nitride, or another liner/diffusion barrier material. In another embodiment of the invention, the second film can be a conductive film such as, e.g., copper.
An example method of the present invention includes the steps of forming a resistor by a damascene process, including defining a trough, depositing a highly resistive film, depositing a dielectric film and polishing to obtain a resistor structure. In one embodiment of the invention, the highly resistive film can be tantalum, xcex1-Ta, tantalum nitride, or another liner/diffusion barrier material.
Another example method of the present invention includes the steps of forming a resistor by a dual-damascene process, including defining a trough and via, depositing a highly resistive film, depositing a dielectric film, and polishing to obtain a resistor structure. In one embodiment of the invention, the first film can be tantalum, tantalum nitride, or another liner/diffusion barrier material.
In one embodiment of the invention, the resistor structure can be a single trough. In another, the resistor structure can include a single trough and a via. In another embodiment, the resistor structure can include a single trough, via and W contact. In yet another, the resistor can include a single trough, via, trough, W via, and W film. In another embodiment a resistor structure can include a plurality of these exemplary resistive elements.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.